Strategic collaborations with Samsung Foundry, Arm and others enable Cadence to deliver pre-validated chiplet solutions based on the Cadence Physical AI chiplet platform.
Cadence has announced a Chiplet Spec-to-Packaged Parts ecosystem to reduce engineering complexity and accelerate time to market for customers developing chiplets targeting physical AI, data center, and high-performance computing (HPC) applications. Initial IP partners joining Cadence include Arm, Arteris, eMemory, M31 Technology, Silicon Creations and Trilinear Technologies, as well as silicon analytics partner proteanTecs. To help reduce risk and streamline customer adoption, Cadence is collaborating with Samsung Foundry to build out a silicon prototype demonstration of the Cadence Physical AI chiplet platform, including pre-integrated partner IP on the Samsung Foundry SF5A process.
Extending their longstanding history of close collaboration, Cadence and Arm are working together to accelerate innovation across physical and infrastructure AI applications. Cadence will leverage the advanced Arm® Zena™ Compute Subsystem (CSS) and other essential IP to enhance Cadence’s Physical AI chiplet platform and Chiplet Framework. The resulting new Cadence solutions accommodate the demanding next-generation edge AI processing requirements for automobiles, robotics and drones, as well as the needs of standards-based I/O and memory chiplets for data center, cloud and HPC applications. The alliances reduce engineering complexities, offer customers a low-risk path to advanced chiplet adoption and pave the way for smarter, safer and more efficient systems.
“Cadence’s new chiplet ecosystem represents a significant milestone in chiplet enablement,” said David Glasco, vice president of the Compute Solutions Group at Cadence. “Multi-die and chiplet-based architectures are increasingly critical to achieving greater performance and cost efficiency amid growing design complexity. Cadence’s chiplet solutions optimize costs, provide customization flexibility and enable configurability. By combining our extensive IP and SoC design expertise with pre-integrated and pre-validated IP from our robust partner ecosystem, Cadence is accelerating the development of chiplet-based solutions and helping customers mitigate risk to quickly realize their chiplet ambitions with greater confidence.”
Cadence has built spec-driven automation to generate chiplet framework architectures that combine Cadence IP and third-party partner IP with chiplet management, security, and safety features, all supported by advanced software. The generated EDA tool flow enables seamless simulation with the Cadence Xcelium Logic Simulator and emulation with the Cadence Palladium Z3 Enterprise Emulation Platform, while the physical design flow employs real-time feedback for efficient place-and-route cycles. The resulting chiplet architectures are standards-compliant to ensure broad interoperability across the chiplet ecosystem, including adherence to the Arm Chiplet System Architecture and future OCP Foundational Chiplet System Architecture. Cadence’s Universal Chiplet Interconnect Express (UCIe™) IP provides industry-standard die-to-die connectivity, while a comprehensive protocol IP portfolio enables fast integration of leading-edge interfaces such as LPDDR6/5X, DDR5-MRDIMM, PCI Express (PCIe®) 7.0, and HBM4
